? semiconductor components industries, llc, 2001 october, 2001 rev. 7 1 publication order number: sn74ls165/d sn74ls165 8-bit parallel-to-serial shift register the sn74ls165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. parallel inputing occurs asynchronously when the parallel load (pl ) input is low. with pl high, serial shifting occurs on the rising edge of the clock; new data enters via the serial data (ds) input. the 2-input or clock can be used to combine two independent clock sources, or one input can act as an active low clock enable. guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 4.75 5.0 5.25 v t a operating ambient temperature range 0 25 70 c i oh output current high 0.4 ma i ol output current low 8.0 ma low power schottky soic d suffix case 751b plastic n suffix case 648 16 1 16 1 soeiaj m suffix case 966 16 1 device package shipping ordering information sn74ls165n 16 pin dip 2000 units/box sn74ls165d soic16 38 units/rail sn74ls165dr2 soic16 2500/tape & reel sn74ls165m soeiaj16 see note 1 sn74ls165mel soeiaj16 1. for ordering information on the eiaj version of the soic package, please contact your local on semiconductor representative. see note 1 http://onsemi.com
sn74ls165 http://onsemi.com 2 connection diagram dip (top view) clock (low-to-high going edge) inputs serial data input asynchronous parallel load (active low) input parallel data inputs serial output from last state complementary output cp 1 , cp 2 ds pl p 0 - p 7 q 7 q 7 0.5 u.l. 0.5 u.l. 1.5 u.l. 0.5 u.l. 10 u.l. 10 u.l. 0.25 u.l. 0.25 u.l. 0.75 u.l. 0.25 u.l. 5 u.l. 5 u.l. notes: a) 1 ttl unit load (u.l.) = 40 a high/1.6 ma low. high low (note a) loading pin names v cc = pin 16 gnd = pin 8 logic symbol note: the flatpak version has the same pinouts (connection diagram) as the dual inline package. 111121314 34 5 6 9 7 10 2 15 d s cp q 7 q 7 pl p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 14 13 12 11 10 9 123456 7 16 15 8 v cc pl cp 2 p 3 p 2 p 1 ds p 0 q 7 cp 1 p 4 p 5 p 6 p 7 q 7 gnd
sn74ls165 http://onsemi.com 3 logic diagram pl cp 1 p 4 p 6 p 5 p 7 cp 2 p 3 p 1 p 2 p 0 d s preset s cp r c l q 0 q 0 preset s cp r c l q 1 q 1 preset s cp r c l q 2 q 2 preset s cp r c l q 3 q 3 preset s cp r c l q 4 q 4 preset s cp r c l q 5 q 5 preset s cp r c l q 6 q 6 preset s cp r c l q 7 q 7 14 1 2 6 3 4 5 11 12 10 13 15 v cc = pin 16 gnd = pin 8 = pin numbers 7 9 functional description the sn74ls165 contains eight clocked master/slave rs flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. parallel data enters when the pl signal is low. the parallel data can change while pl is low, provided that the recommended setup and hold times are observed. for clock operation, pl must be high. the two clock inputs perform identically; one can be used as a clock inhibit by applying a high signal. to avoid double clocking, however, the inhibit signal should only go high while the clock is high. otherwise, the rising inhibit signal will cause the same response as a rising clock edge. the flip-flops are edge-triggered for serial operations. the serial input data can change at any time, provided only that the recommended setup and hold times are observed, with respect to the rising edge of the clock. truth table pl cp contents response pl 1 2 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 response l x x p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 parallel entry h l d s q 0 q 1 q 2 q 3 q 4 q 5 q 6 right shift h h q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 no change h l d s q 0 q 1 q 2 q 3 q 4 q 5 q 6 right shift h h q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 no change h = high voltage level l = low voltage level x = immaterial
sn74ls165 http://onsemi.com 4 dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 0.65 1.5 v v cc = min, i in = 18 ma v oh output high voltage 2.7 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table v ol out p ut low voltage 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v in v il or v ih v ol output low voltage 0.35 0.5 v i ol = 8.0 ma v in = v il or v ih per truth table i ih input high current other inputs pl input 20 60 m a v cc = max, v in = 2.7 v i ih other inputs pl input 0.1 0.3 ma v cc = max, v in = 7.0 v i il input low current other inputs pl input 0.4 1.2 ma v cc = max, v in = 0.4 v i os short circuit current (note 2) 20 100 ma v cc = max i cc power supply current 36 ma v cc = max 2. not more than one output should be shorted at a time, nor for more than 1 second. ac characteristics (t a = 25 c) limits symbol parameter min typ max unit test conditions f max maximum input clock frequency 25 35 mhz t plh t phl propagation delay pl to output 22 22 35 35 ns t plh t phl propagation delay clock to output 27 28 40 40 ns v cc = 5.0 v c l = 15 p f t plh t phl propagation delay p 7 to q 7 14 21 25 30 ns c l = 15 pf t plh t phl propagation delay p 7 to q 7 21 16 30 25 ns ac setup requirements (t a = 25 c) limits symbol parameter min typ max unit test conditions t w cp clock pulse width 25 ns t w pl pulse width 15 ns t s parallel data setup time 10 ns t s serial data setup time 20 ns v cc = 5.0 v t s cp 1 to cp 2 setup time 1 30 ns cc t h hold time 0 ns t rec recovery time, pl to cp 45 ns 1 the role of cp 1 and cp 2 in an application may be interchanged.
sn74ls165 http://onsemi.com 5 definition of terms: setup time (t s ) e is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from low-to-high in order to be recognized and transferred to the outputs. hold time (t h ) e is defined as the minimum time following the clock transition from low-to-high that the logic level must be maintained at the input in order to ensure continued recognition. a negative hold time indicates that the correct logic level may be released prior to the clock transition from low-to-high and still be recognized. recovery time (t rec ) e is defined as the minimum time required between the end of the pl pulse and the clock transition from low-to-high in order to recognize and transfer loaded data to the q outputs. ac waveforms t w 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v cp 1 cp 2 q 7 or q 7 p n pl or cp t phl t plh pl cp t rec q 7 or q 7 pl t phl t plh t w t w 1/f max t s t s(h) t h(h) t s(l) t h(l) figure 1. figure 2. 1.3 v figure 3. figure 4.
sn74ls165 http://onsemi.com 6 package dimensions n suffix plastic package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
sn74ls165 http://onsemi.com 7 package dimensions d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
sn74ls165 http://onsemi.com 8 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z m suffix soeiaj package case 96601 issue o on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. sn74ls165/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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